1. Field of the Invention
Disclosed embodiments relate to coupled spiral planar inductors.
2. Description of the Related Art
Input signals and power are provided to an integrated circuit from a semiconductor package through a series of bump pads. Capacitance associated with the circuitry behind these bump pads is known to introduce significant discontinuities at a die-package interface. These discontinuities greatly degrade the system performance, so that even if the package and associated printed circuit board (PCB) are well-designed, the return loss and insertion loss of the system can be significantly enhanced. If the system loss is large enough, the system loss can lead to possible system specification violations, and the overall system may not deliver the specified amount of performance.
One traditional method used to mitigate the effect of the on-die excess signal capacitance of the integrated circuit can be implemented by using an inductor coil on die to resonate away excess on die signal capacitance. These inductors can require a large amount of silicon space. Likewise, the inductors can add ohmic loss to a signal path as interconnects on die can be lossy. Since excess on die signal capacitance can result in a closed eye at a receiver, the power supply voltage can be increased to open the eye at the receiver. Such a voltage increase, however, can result in additional power dissipation.
FIG. 1 illustrates a perspective-view of an apparatus 100 with an increased power rail voltage to open eye aperture at a receiver. As shown, there is a die pad 102. In some situations, on die excess capacitance of the signal, often due to die electrostatic discharge circuitry (ESD) can represent discontinuity for a digital communication channel. This may in turn reduce eye height (voltage), reduce noise margin, and increase jitter at the receiver.